Typical dynamic bit lines use a pre-charge phase, followed by the evaluate phase, in every cycle. This consumes substantial power, as usually the clock signal CLK acts as the pre-charge, and the clock signal is of course coming in every cycle. When there is no evaluate for a long time, then the dynamic bit lines stay in pre-charge; however, that also causes substantial leakage power through the register array cell's pull-down transistors (usually 8 or 16 cells dotted together—that is, the bit line for each cell is electrically connected). Numerous techniques have been proposed to reduce the active power of dynamic READ, but in scenarios where the array will not be accessed for a long time, the leakage power can be substantial as well.
US Patent Publication number 2006-0098474 of Dang et al. discloses a high performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode. In one embodiment, the SRAM device includes (1) a set of memory cells and (2) biasing circuitry, coupled to the set, configured to bias a subset of the set based on a memory address associated therewith.
U.S. Pat. No. 7,061,794 of Sabharwal et al. discloses a word-line-based source-biasing scheme for reducing memory cell leakage. In standby mode, word lines are deselected and a source-biasing potential is provided to SRAM cells. In read mode, a selected word line deactivates the source-biasing potential provided to the selected row of SRAM cells, whereas the remaining SRAM cells on the selected bit line column continue to be source-biased.
U.S. Pat. No. 5,581,500 of D'Souza discloses a memory cell with power supply induced reversed-bias pass transistors for reducing off-leakage current. The memory cell operates within a power supply range that induces the pass transistor(s) of the memory cell to be reversed biased when the memory cell is not being accessed. The memory cell includes a storage element capable of storing either a first data value or a second data value; a pass transistor, coupled to the storage element; and a power supply generator coupled to the storage element. The power supply generator is configured to generate supply level voltages for the storage element so as to induce the pass transistor into a substantially reverse-biased state when the storage element is not being accessed, regardless of whether the storage element is storing the first data value or a second data value.